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SI9150
Vishay Siliconix
SI9150
Synchronous Buck Converter Controller
FEATURES
* 6- to 16.5-V Input Range (SI9150CY) * Voltage-Mode PWM Control * Low-Current Standby Mode * Enable Control * Dual 100-mA Output Drivers * 2% Band Gap Reference * Multiple Converters Easily Synchronized * Over-Current Protection
DESCRIPTION
The SI9150 synchronous buck regulator controller is ideally suited for high-efficiency step down converters in batterypowered equipment. Combined with the Si9943DY MOSFET half-bridge, a 90% efficient, 7.5-W, 3.3-V or 5-V power supply can be implemented using standard surface- mount assembly techniques. The wide input range allows operation from NiCd or NiMH battery packs using six to ten cells. Over-current protection is achieved by sensing the on-state voltage drop across the high side p-channel MOSFET, which eliminates the need for a current sense resistor. Duty ratios of 0 to 100% and switching frequencies up to 300 kHz are possible. The IC can be disabled by pulling EN low (IDD = 100 A), or the 2.5-V reference can be maintained, with all other functions disabled, by pulling STBY low (IDD = 500 A). The SI9150 is available in a 14-pin SOIC and rated for the commercial temperature range of 0 to 70C (C suffix), and the industrial temperature range of -40 to +85C (D suffix).
FUNCTIONAL BLOCK DIAGRAM
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SI9150
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to GND. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V ISENSE Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2 V to VDD +2 V All Other Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VDD + 0.3 V P-Gate, N-Gate Continuous Source/Sink Current . . . . . . . . . . .50 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 125C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150C Power Dissipation (Package)a 14-Pin SOIC (Y Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Thermal Impedance (JA) 14-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 7.2 mW/C.
SPECIFICATIONSa
Limits Test Conditions Unless Otherwise Specified Parameter Reference
Output Voltage VREF TA = 25C Measured at Feedbacke Pin 5 TMIN to TMAXd 2.45 2.425 2.50 2.500 2.55 2.575 2.45 2.40 2.50 2.500 2.55 2.60 V C Suffix 0 to 70C 6.0 VDD 16.5 V
Limits
D Suffix -40 to 85C
Symbol
Minb
Typc
Maxb
Minb
Typc
Maxb
Unit
Oscillator
Maximum Frequency Initial Accuracy Oscillator Ramp Amplitude Temperature Stabilityd fMAX fOSC VOSC fTEMP COSC = 94.3 pF, ROSC = 28.7 k TA = 25Cf COSC = 212 pF, ROSC = 41.2 k TA = 25Cf TA = 25C, 100 kHz VDD = 10 V, TMIN to TMAX 255 85 2.05 -5 300 100 2.65 3 345 115 2.85 +5 255 85 2.05 -6 300 100 2.65 4 345 kHz 115 2.85 +6 V %
Error Amplifier
Input BIAS Current Open Loop Voltage Gain Offset Voltage Unity Gain Bandwidthd Output Current Power Supply Rejection
d
IB AVOL VOS BW IOUT PSRR
VFB = VREF 60
25 72 10 1 1.5 -0.30 1 50 2.5 70
500 58 25 1 -0.20 0.9 48
25 72 10 1.5 -0.30 2.5 70
750
nA dB
30
mV MHz
Source, VCOMP = 2.50 V Sink, VCOMP = 1.0 V
-0.15
mA dB
Protection
Current Limit Threshold Voltage Current Limit Delay to Outputd Undervoltage Lockout Voltage Undervoltage Hysteresis Softstart Pull-Up Current VCL td V UVLO VHYS ISS TA = 25C, VDD = 10 V TA = 25C Upper Threshold 5.4 0.10 0.43 0.49 500 5.7 0.17 20 0.55 1000 6.0 0.25 5.38 0.10 0.43 0.49 500 5.7 0.17 20 0.55 1000 6.01 0.26 V ns V A
Supply
Supply Current (Enable Low) Supply Current (Enable High) Supply Current (STBY Low) IOFF ICC ISB CL = 0 pF, fOSC = 100 kHz VDD = 10 V 60 2.2 300 100 3.0 500 60 2.2 300 100 3.0 550 A mA A
S-60752--Rev. E, 5-Apr-99 2
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SI9150
Vishay Siliconix
SPECIFICATIONSa
Limits Test Conditions Unless Otherwise Specified Parameter Output
Output High Voltage Output Low Voltage Output Resistance Rise Timed Fall Timed VOH VOL ROUT tr tf IOUT = 10 mA, VDD = 10 V IOUT = -10 mA, VDD = 10 V IOUT = 100 mA, VDD = 10 V CL = 800 pF, VDD = 10 V 10 30 30 9.75 0.25 20 60 60 10 30 30 9.7 0.3 25 70 70 V ns C Suffix 0 to 70C 6.0 VDD 16.5 V
Limits
D Suffix -40 to 85C
Symbol
Minb
Typc
Maxb
Minb
Typc
Maxb
Unit
Logic
Delay to Output Enable Pull-Up Resistance STBY Pull-Up Current Turn-On Threshold Turn-Off Threshold Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. Guaranteed by design, not subject to production test. e. The voltage reference is trimmed with the feedback (Pin 5) connected to compensation (Pin 4) so that the effect of the error amplifier's input offset voltage is eliminated. f. COSC includes the PC board's parasitic capacitance. td(EN) REN ISTBY VENH VENL TA = 25C, VSTBY = 0 V VDD = 10 V VDD = 10 V, Rising Input Voltage VDD = 10 V, Falling Input Voltage -25 6 2 Transition High to Low 0.25 500 -20 6.8 3.75 -15 8 5 -28 6 2 1 0.25 500 -20 6.8 3.75 -12 8 5 1 s k A V
TYPICAL CHARACTERISTICS
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SI9150
Vishay Siliconix
PIN CONFIGURATION
PIN DESCRIPTION
Pin 1: EN When this pin is low, the IC is shut down. After a low signal is applied to EN, then COMP, REF, RT, and CT settle toward ground; N-GATE, STBY and Soft-Start are grounded; and PGATE is pulled high. The current consumption is no more than 100 A in this state. This input's threshold has substantial hysteresis so that a capacitor to GND can be used to delay restart after the current limit is activated. After VENH is exceeded, one clock cycle elapses before N-GATE and PGATE are enabled. EN is pulled up to VDD through a 500-k resistor and is pulled down internally when the current limit is triggered. Pin 2: STBY Has a function similar to EN. The differences are that the EN pin is unaffected, that the reference is still available, that bias currents are still present internally, and that this pin's pull up current is present. This pin should be used to disable an application if the reference voltage is still needed. Pin 3: Soft-Start (SS) This pin limits the maximum voltage that the error amplifier can output. A capacitor between this pin and ground will limit the rate at which the duty factor can increase during initial power up, during a restart when EN or STBY goes high, or after the current limit is triggered. A capacitor here can prevent an application from triggering the SI9150's current limit during startup. Soft-Start is pulled low if either EN or STBY is low. Pin 4: Compensation (COMP) This pin is tied directly to the output of the error amplifier. The feedback network which insures the stability of an application uses this pin. COMP settles low when either EN or STBY is pulled low. Pin 5: Feedback (FB) This pin is attached directly to the inverting input of the error amplifier. This pin is used to regulate the power supply's output voltage. Pin 6: Reference (VREF) The internal 2.5-V reference generator is attached to this pin through a 5- resistor. A 0.1-F bypass capacitor is needed to suppress noise. Also note that the generator has an open emitter; it will not pull down. The maximum current that the generator will source before it current limits is about 10 mA. Many parts of the IC use this voltage, so it is important not to overload the reference generator. Pin 7: ISENSE This pin should be attached to the switched node (the drains of the application's p-channel and n-channel MOSFETs). If the voltage between VDD and this pin is more then 0.46 V while the P-GATE is low, the current limit is activated. The current limit is relatively slow to prevent false triggering due to noise. Activating the current limit causes EN to be pulled to GND. ISENSE may be operated from VDD + 2 V to GND - 2 V. For operation above 13.5 VDD a filter (1 k, 33 pF) is needed between the MOSFET drains and the ISENSE pin; refer to Figure 1. Pin 8: SYNC This pin forces the clock to reset when low, and is also pulled low when the clock resets itself. Thus if several SI9150's have their sync pins shorted together, they will be synchronized; the shortest duration clock will control the other clocks.
S-60752--Rev. E, 5-Apr-99 4
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SI9150
Vishay Siliconix
Pin 9: CT A capacitor from this pin to ground is charged until it reaches 2.5 V, at which point the capacitor is rapidly discharged. The resulting sawtooth with about 1 V added is compared to the input voltage at COMP to determine whether P-GATE and NGATE should be high or low. The maximum recommended value for COSC is 200 pF (See Typical Characteristics). The capacitor's charging current is controlled by Pin 10, RT. Pin 10: RT The IC applies 2.5 V to this pin, and the current is mirrored and applied to Pin 9 while charging the capacitor. The minimum recommended value of ROSC is 20 k (Figure 1). Pin 11: GND Since the SI9150 has a high-side current limit, it is important that VDD track the voltage on the source of the p-channel power MOSFET. For noise immunity, it is best to separate the logic ground from the power ground. The logic ground should be decoupled to VDD through at least a 1-F capacitor. The two grounds may be connected by a path that is long Pin 14: VDD This pin powers the IC. The connection between this pin and the source of the p-channel FET should be as short as practical. Read Pin 11's description for bypassing suggestions. compared to the the path from VDD to the source of the application's p-channel MOSFET. Pin 12: N-GATE This pin is used to drive the application's n-channel MOSFET. When turning the n-channel MOSFET off, the p-channel MOSFET will not be turned on until N-GATE is within a few volts of ground. This pin is low while either EN or STBY is low. Pin 13: P-GATE This pin is used to drive the application's p-channel MOSFET. The break before make circuitry for the P-GATE is complimentary to that for the N-GATE. This pin is high while either EN or STBY is low.
APPLICATIONS
FIGURE 1. Typical Application Circuit
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